By Manuel Hohenauer

ISBN-10: 3540719814

ISBN-13: 9783540719816

C Compilers for ASIPs: computerized Compiler new release with LISA

by:

Manuel Hohenauer

Rainer Leupers

The ever expanding complexity and function requisites of recent digital units are altering the way in which embedded platforms are designed and carried out this day. the present development is in the direction of programmable System-on-Chip structures which hire progressively more program particular Instruction-set Processors (ASIPs) as development blocks. ASIP layout structures contain retargetable software program improvement instruments that may be tailored fast to various objective processor configurations. Such instruments are typically pushed by way of a processor version given in an structure Description Language (ADL), akin to LISA. one of many significant demanding situations during this context is retargetable compilation for high-level programming languages like C. firstly, an ADL needs to catch the architectural details wanted for the device iteration in an unambiguous and constant method. this can be quite tricky for compiler and instruction-set simulator. in addition, there exists a trade-off among the compiler's flexibility and the standard of compiled code.

This ebook provides a singular technique for ADL-based instruction-set description with a view to permit the automated retargeting of the whole software program toolkit from a unmarried ADL processor version. also, this e-book comprises retargetable optimization strategies for architectures with SIMD and Predicated Execution aid. either permits a excessive speedup in compiler new release and combines excessive flexibility with applicable code caliber while. assurance incorporates a complete evaluate of retargetable compilers and ADL established processor layout, a strategy and similar toolkit to generate a C-compiler totally instantly from an ADL processor version, and retargetable code optimization options.

  • Presents a robust history and diverse views of structure description language (ADL)-based processor layout and the retargetable compilation problem;
  • Provides the background of ADL established processor layout, making the reader acquainted with the prior study in addition to the problems confronted over time;
  • Offers an ADL established modelling formalism and corresponding implementation equipment, that are used for automated compiler retargeting to quick receive compiler help for newly built ASIPs;
  • Presents retargetable optimization strategies for universal ASIP good points, which might be fast tailored to various objective processor configurations and aid to fulfill the stringent functionality necessities of embedded applications.

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Extra info for C Compilers for ASIPs: Automatic Compiler Generation with LISA

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For instance, storage units such as registers or memory must be explicitly declared. Furthermore, it is assumed that each instruction is executed in one machine cycle; there is no pipeline modeling. The language is used by the instruction-set simulator called SIGH/SIM [8] and the retargetable code generator CBC [9, 162]. It is also used by the instruction-set simulator CHECKERS [273] and the code generator CHESS [69] developed at the IMEC institute [118]. These tools have later been commercialized and are now available from Target Compiler M.

Each behavior is described using a so-called stage that corresponds usually to a pipeline stage. Sequentiality and concurrency is specified within or between stages. So far, AIDL was only employed to model three processors, which are all based on the PA-RISC instruction-set architecture [114]. As described in [253], it is possible to generate a synthesizable HDL code and a simulator from an AIDL specification. So far, support for compiler, assembler, and linker generation is not available. UDL/I: The UDL/I language [264] is also an RT-level hardware description language, but in contrast to MIMOLA mainly intended for compiler generation.

Other examples include CoSy [38], LANCE [222], SPAM [247], and SUIF [249]. Some of them constitute a key component of the ASIP design environments discussed in Chapter 4. A comprehensive survey of retargetable compilers can be found in [224]. 5 Synopsis • Compilers can be coarsely separated into a frontend and a target-specific backend (code selector, scheduler, register allocator). • Retargetable compilers can be quickly adapted to varying processor configurations. , an ADL model). Chapter 4 Related Work In general, ADL design must trade-off the level of abstraction vs.

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